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Military & Space Products
32K x 8 STATIC RAM
FEATURES
RADIATION * Fabricated with RICMOSTM IV Bulk 0.8 m Process (Leff = 0.65 m) * Total Dose Hardness through 1x106 rad(SiO2) * Neutron Hardness through 1x1014 cm-2 * Dynamic and Static Transient Upset Hardness through 1x109 rad(Si)/s * Soft Error Rate of <1x10-10 upsets/bit-day * Dose Rate Survivability through 1x1012 rad(Si)/s * Latchup Free OTHER
HC6856
* Listed on SMD #5962-92153. Available as MIL-PRF-38535 QML Class Q and Class V * Read/Write Cycle Times 30 ns (Typical) 40 ns (-55 to 125C) * Standby Current of 20 A (typical) * Asynchronous Operation * CMOS or TTL Compatible I/O * Single 5 V 10% Power Supply * Packaging Options - 36-Lead Flat Pack (0.630 in. x 0.650 in.) - 28-Lead Flat Pack (0.530 in. x 0.720 in.) - 28-Lead DIP, MIL-STD-1835, CDIP2-T28
GENERAL DESCRIPTION
The 32K x 8 Radiation Hardened Static RAM is a high performance 32,768 x 8-bit static random access memory with industry-standard functionality. It is fabricated with Honeywell's radiation hardened technology, and is designed for use in systems operating in radiation environments. The RAM operates over the full military temperature range and requires only a single 5 V 10% power supply. The RAM is available with either TTL or CMOS compatible I/O. Power consumption is typically less than 50 mW/MHz in operation, and less than 5 mW/MHz in the low power disabled mode. The RAM read operation is fully asynchronous, with an associated typical access time of 20 ns. Honeywell's enhanced RICMOSTM IV (Radiation Insensitive CMOS) technology is radiation hardened through the use of advanced and proprietary design, layout, and process hardening techniques. The RICMOSTM IV process is a 5-volt, twin-well CMOS technology with a 170 A gate oxide and a minimum drawn feature size of 0.8 m (0.65 m effective gate length--Leff). Additional features include a three layer interconnect metalization and a lightly doped drain (LDD) structure for improved short channel reliability. High resistivity cross-coupled polysilicon resistors have been incorporated for single event upset hardening.
HC6856
FUNCTIONAL DIAGRAM
A:0-8,12-13 Row Decoder
* * *
11
32,768 x 8 Memory Array
* * *
CE NCS NWE
Column Decoder Data Input/Output
WE * CS * CE
8 8 DQ:0-7
NOE
CS * CE
NWE * CS * CE * OE (0 = high Z)
Signal
1 = enabled # Signal
A:9-11,14
4
All controls must be enabled for a signal to pass. (#: number of buffers, default = 1)
SIGNAL DEFINITIONS
A: 0-14 DQ: 0-7 NCS Address input pins (A) which select a particular eight-bit word within the memory array. Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write operation. Negative chip select, when at a low level allows normal read or write operation. When at a high level it forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers. If this signal is not used it must be connected to VSS. Negative write enable, when at a low level activates a write operation and holds the data output drivers in a high impedance state. When at a high level it allows normal read operation. Negative output enable, when at a high level holds the data output drivers in a high impedance state. When at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must be connected to VSS. Chip enable, when at a high level allows normal operation. When at a low level it forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers. If this signal is not used it must be connected to VDD.
NWE NOE
CE
TRUTH TABLE
NCS L L H X CE H H X L NWE H L XX XX NOE L X XX XX MODE Read Write Deselected Disabled DQ Data Out Data In High Z High Z
Notes: X: VI=VIH or VIL XX: VSSVIVDD NOE=H: High Z output state maintained for NCS=X, CE=X, NWE=X
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HC6856
RADIATION CHARACTERISTICS
Total Ionizing Radiation Dose The RAM will meet all stated functional and electrical specifications over the entire operating temperature range after the specified total ionizing radiation dose. All electrical and timing performance parameters will remain within specifications after rebound at VDD = 5.5 V and T =125C extrapolated to ten years of operation. Total dose hardness is assured by wafer level testing of process monitor transistors and RAM product using 10 keV X-ray radiation. Transistor gate threshold shift correlations have been made between 10 keV X-rays applied at a dose rate of 1x105 rad(SiO2)/min at T = 25C and gamma rays (Cobalt 60 source) to ensure that wafer level X-ray testing is consistent with standard military radiation test environments. The RAM will meet any functional or electrical specification after exposure to a radiation pulse of 50 ns duration up to 1x1012 rad(Si)/s, when applied under recommended operating conditions. Note that the current conducted during the pulse by the RAM inputs, outputs, and power supply may significantly exceed the normal operating levels. The application design must accommodate these effects.
Neutron Radiation The RAM will meet any functional or timing specification after a total neutron fluence of up to 1x1014 cm-2 applied under recommended operating or storage conditions. This assumes an equivalent neutron energy of 1 MeV.
Transient Pulse Ionizing Radiation The RAM is capable of writing, reading, and retaining stored data during and after exposure to a transient ionizing radiation pulse of 1 s duration up to 1x109 rad(Si)/s, when applied under recommended operating conditions. To ensure validity of all specified performance parameters before, during, and after radiation (timing degradation during transient pulse radiation is 10%), it is suggested that a minimum of 0.8 F per part of stiffening capacitance be placed between the package (chip) VDD and VSS, with a maximum inductance between the package (chip) and stiffening capacitance of 0.7 nH per part. If there are no operate-through or valid stored data requirements, the capacitance specification can be reduced to a minimum of 0.1 F per part.
Soft Error Rate The RAM is capable of soft error rate (SER) performance of <1x10-10 upsets/bit-day, under recommended operating conditions. This hardness level is defined by the Adams 10% worst case cosmic ray environment.
Latchup The RAM will not latch up due to any of the above radiation exposure conditions when applied under recommended operating conditions. Fabrication with the RICMOSTM p-epi on p+ substrate process and use of proven design techniques, such as double guardbanding, ensure latchup immunity.
RADIATION HARDNESS RATINGS (1)
Limits (2) 1x106 1x109 1x1012 <1x10-9 (4) <1x10-10 1x1014 N/cm2
1 MeV equivalent energy, Unbiased, TA=25C
Parameter Total Dose Transient Dose Rate Upset (3) Transient Dose Rate Survivability Soft Error Rate: Level A Level Z Neutron Fluence
(1) (2) (3) (4)
Units rad(SiO2) rad(Si)/s rad(Si)/s upsets/bit-day
Test Conditions
TA=25C Pulse width1 s Pulse width50 ns, X-ray, VDD=6.6 V, TA=25C Adams 10% worst case environment
Device will not latch up due to any of the specified radiation exposure conditions. Operating conditions (unless otherwise specified): VDD=4.5 V to 5.5 V, TA=-55C to 125C. Suggested stiffening capacitance specifications for optimum expected dose rate upset performance is stated above in the text. SER <1x10-10 u/b-d from -55 to 80C.
3
HC6856
ABSOLUTE MAXIMUM RATINGS (1)
Rating Symbol VDD VPIN TSTORE TSOLDER PD IOUT VPROT Parameter Positive Supply Voltage (2) Voltage on Any Pin (2) Storage Temperature (Zero Bias) Soldering Temperature * Time Total Package Power Dissipation (3) DC or Average Output Current ESD Input Protection Voltage (4) Thermal Resistance (Jct-to-Case) 28 FP/36 FP 28 DIP TJ Junction Temperature 2000 2 10 175 Min -0.5 -0.5 -65 Max 7.0 VDD+0.5 150 270*5 2.5 25 Units V V C C*s W mA V C/W C/W C
JC
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability. (2) Voltage referenced to VSS. (3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this specification. (4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.
RECOMMENDED OPERATING CONDITIONS
Description Symbol VDD TA VPIN Parameter Supply Voltage (referenced to VSS) Ambient Temperature Voltage on Any Pin (referenced to VSS) Min 4.5 -55 -0.3 Typ 5.0 25 Max 5.5 125 VDD+0.3 Units V C V
CAPACITANCE (1)
Worst Case Symbol CI CO Parameter Input Capacitance Output Capacitance Typical 4 6.5 Max 6 8 Units pF pF Test Conditions
VI=VDD or VSS, f=1 MHz VIO=VDD or VSS, f=1 MHz
(1) This parameter is tested during initial design characterization only.
DATA RETENTION CHARACTERISTICS
Symbol VDR IDR Parameter (2) Data Retention Voltage (3) Data Retention Current Typical (1) 2.0 150 Worst Case Min 2.5 400 Max V A
NCS=VDR VI=VDR or VSS NCS=VDD=VDR VI=VDR or VSS
Units
Test Conditions
(1) Typical operating conditions: TA= 25C, pre-radiation. (2) Worst case operating conditions: TA= -55C to +125C, post total dose at 25C. (3) To maintain valid data storage during transient radiation, VDD must be held within the recommended operating range.
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HC6856
DC ELECTRICAL CHARACTERISTICS
Symbol IDDSB1 IDDSB2 IDDOPW IDDOPR II IOZ VIL Parameter Static Supply Current Static Supply Current with Chip Disabled Dynamic Supply Current, Selected (Write) Dynamic Supply Current, Selected (Read) Input Leakage Current Output Leakage Current Low-Level InputVoltage CMOS TTL CMOS TTL Typical Worst Case (2) Units (1) Min Max 0.02 0.02 5.5 4.5 0.05 0.1 1.9 1.3 3.0 1.7 0.2
0.7xVDD
Test Conditions (3)
VIH=VDD IO=0 VIL=VSS Inputs Stable CE=VSS or NCS=VDD IO=0, VSS VIVDD (4) f=1 MHz, IO=0, CE=VIH=VDD NCS=VIL=VSS (5) f=1 MHz, IO=0, CE=VIH=VDD NCS=VIL=VSS (5) VSSVIVDD VSSVIOVDD Output=high Z VDD=4.5V VDD=4.5V VDD=5.5V VDD=5.5V VDD=4.5V, IOL=10 mA VDD=4.5V, IOL=200 A VDD=4.5V, IOH=-5 mA VDD=4.5V, IOH=-200 A
1.2 1.2 7.5 6.5 -5 -10 +5 10
0.3xVDD
mA mA mA mA A A V V V V
0.8
VIH
High-Level Input Voltage
2.2 0.4 0.05 4.2
VDD-0.05
VOL
Low-Level Output Voltage
V V V V
4.8 VOH
(1) (2) (3) (4) (5)
High-Level Output Voltage
Typical operating conditions: VDD= 5.0 V,TA=25C, pre-radiation. Worst case operating conditions: VDD=4.5 V to 5.5 V, TA=-55C to +125C, post total dose at 25C. Input high = VIH VDD-0.3V, input low =VIL 0.3V Guaranteed but not tested. All inputs switching. DC average current.
2.9 V Vref1 249 DUT output Vref2
+ -
Valid high output
+ -
Valid low output
CL >50 pF* *CL = 5 pF for TWLQZ, TSHQZ, TELQZ, and TGHQZ
Tester Equivalent Load Circuit
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HC6856
READ CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3) Symbol Parameter Typical (2) TAVAVR TAVQV TAXQX TSLQV TSLQX TSHQZ TEHQV TEHQX TELQZ TGLQV TGLQX TGHQZ Address Read Cycle Time Address Access Time Address Change to Output Invalid Time Chip Select Access Time Chip Select Output Enable Time Chip Select Output Disable Time Chip Enable Access Time Chip Enable Output Enable Time Chip Enable Output Disable Time Output Enable Access Time Output Enable Output Enable Time Output Enable Output Disable Time 18 18 15 20 20 6 20 20 6 4 3 4 0 10 16 10 10 16 10 40 5 40 -55 to 125C Min 40 40 Max ns ns ns ns ns ns ns ns ns ns ns ns Units
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading CL >50 pF, or equivalent capacitive output loading CL=5 pF for TSHQZ, TELQZ TGHQZ. For CL >50 pF, derate access times by 0.02 ns/pF (typical). (2) Typical operating conditions: VDD=5.0 V, TA=25C, pre-radiation. (3) Worst case operating conditions: VDD=4.5 V to 5.5 V, post total dose at 25C.
TAVAVR
ADDRESS
TAVQV TSLQV TAXQX
NCS
TSLQX TSHQZ DATA VALID
DATA OUT
HIGH IMPEDANCE TEHQX TEHQV
TELQZ
CE
TGLQX TGLQV TGHQZ
NOE
(NWE = high)
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HC6856
WRITE CYCLE AC TIMING CHARACTERISTICS (1)
Symbol Parameter Typical (2) Worst Case (3) SER <1E-9 (4) SER <1E-10 Min Max Min Max 40 35 35 30 35 0 0 0 0 5 5 35 10 60 55 55 50 55 0 0 0 0 5 5 55 10
Units ns ns ns ns ns ns ns ns ns ns ns ns
TAVAVW Write Cycle Time (5) TWLWH TSLWH TDVWH TAVWH TWHDX TAVWL TWHAX TWLQZ TWHQX TWHWL TEHWH Write Enable Write Pulse Width Chip Select to End of Write Time Data Valid to End of Write Time Address Valid to End of Write Time Data Hold Time after End of Write Time Address Valid Setup to Start of Write Time Address Valid Hold after End of Write Time Write Enable to Output Disable Time Write Disable to Output Enable Time Write Disable to Write Enable Pulse Width Chip Enable to End of Write Time
30 25 25 20 25 0 0 0 5 15 4 25
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading0 pF, or equivalent capacitive load of 5 pF for TWLQZ. (2) Typical operating conditions: VDD=5.0 V, TA=25C, pre-radiation. (3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 125C, post total dose at 25C. (4) SER 1E-10 u/b-d from -55 to 80. (5) TAVAVW= TWLWH + TWHWL
TAVAVW
ADDRESS
TAVWH TAVWL TWHWL TWLWH TWHAX
NWE
TWLQZ TWHQX
DATA OUT
HIGH IMPEDANCE
TDVWH DATA VALID TSLWH
TWHDX
DATA IN
NCS
TEHWH
CE
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HC6856
DYNAMIC ELECTRICAL CHARACTERISTICS
Read Cycle The RAM is asynchronous in operation, allowing the read cycle to be controlled by address, chip select (NCS), or chip enable (CE) (refer to Read Cycle timing diagram). To perform a valid read operation, both chip select and output enable (NOE) must be low and chip enable and write enable (NWE) must be high. The output drivers can be controlled independently by the NOE signal. Consecutive read cycles can be executed with NCS held continuously low, and with CE held continuously high. For an address activated read cycle, NCS and CE must be valid prior to or coincident with the activating address edge transition(s). Any amount of toggling or skew between address edge transitions is permissible; however, data outputs will become valid TAVQV time following the latest occurring address edge transition. The minimum address activated read cycle time is TAVAV. When the RAM is operated at the minimum address activated read cycle time, the data outputs will remain valid on the RAM I/O until TAXQX time following the next sequential address transition. To control a read cycle with NCS, all addresses and CE must be valid prior to or coincident with the enabling NCS edge transition. Address or CE edge transitions can occur later than the specified setup times to NCS; however, the valid data access time will be delayed. Any address edge transition, which occurs during the time when NCS is low, will initiate a new read access, and data outputs will not become valid until TAVQV time following the address edge transition. Data outputs will enter a high impedance state TSHQZ time following a disabling NCS edge transition. To control a read cycle with CE, all addresses and NCS must be valid prior to or coincident with the enabling CE edge transition. Address or NCS edge transitions can occur later than the specified setup times to CE; however, the valid data access time will be delayed. Any address edge transition which occurs during the time when CE is high will initiate a new read access, and data outputs will not become valid until TAVQV time following the address edge transition. Data outputs will enter a high impedance state TELQZ time following a disabling CE edge transition. Write Cycle The write operation is synchronous with respect to the address bits, and control is governed by write enable (NWE), chip select (NCS), or chip enable (CE) edge transitions (refer to Write Cycle timing diagrams). To perform a write operation, both NWE and NCS must be low, and CE must be high. Consecutive write cycles can be performed with NWE or NCS held continuously low, or CE held continuously high. At least one of the control signals must transition to the opposite state between consecutive write operations. The write mode can be controlled via three different control signals: NWE, NCS, and CE. All three modes of control are similar except the NCS and CE controlled modes actually disable the RAM during the write recovery pulse. Only the NWE controlled mode is shown in the table and diagram on the previous page for simplicity; however, each mode of control provides the same write cycle timing characteristics. Thus, some of the parameter names referenced below are not shown in the write cycle table or diagram, but indicate which control pin is in control as it switches high or low. To write data into the RAM, NWE and NCS must be held low and CE must be held high for at least TWLWH/TSLSH/ TEHEL time. Any amount of edge skew between the signals can be tolerated, and any one of the control signals can initiate or terminate the write operation. For consecutive write operations, write pulses must be separated by the minimum specified TWHWL/TSHSL/TELEH time. Address inputs must be valid at least TAVWL/TAVSL/TAVEH time before the enabling NWE/NCS/CE edge transition, and must remain valid during the entire write time. A valid data overlap of write pulse width time of TDVWH/TDVSH/TDVEL, and an address valid to end of write time of TAVWH/ TAVSH/TAVEL also must be provided for during the write operation. Hold times for address inputs and data inputs with respect to the disabling NWE/NCS/CE edge transition must be a minimum of TWHAX/TSHAX/TELAX time and TWHDX/TSHDX/TELDX time, respectively. The minimum write cycle time is TAVAV.
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HC6856
TESTER AC TIMING CHARACTERISTICS
TTL I/O Configuration
3V
CMOS I/O Configuration
VDD-0.5 V
Input Levels*
1.5 V 0V 0.5 V
VDD/2
1.5 V
VDD/2
Output Sense Levels
High Z
VDD-0.4V 0.4 V 3.4 V 2.4 V
High Z
VDD-0.4V 0.4 V 3.4 V High Z 2.4 V
High Z
High Z = 2.9V
High Z = 2.9V
* Input rise and fall times <1 ns/V
QUALITY AND RADIATION HARDNESS ASSURANCE
Honeywell maintains a high level of product integrity through process control, utilizing statistical process control, a complete "Total Quality Assurance System," a computer data base process performance tracking system, and a radiation hardness assurance strategy. The radiation hardness assurance strategy starts with a technology that is resistant to the effects of radiation. Radiation hardness is assured on every wafer by irradiating test structures as well as SRAM product, and then monitoring key parameters which are sensitive to ionizing radiation. Conventional MIL-STD-883 TM 5005 Group E testing, which includes total dose exposure with Cobalt 60, may also be performed as required. This Total Quality approach ensures our customers of a reliable product by engineering in reliability, starting with process development and continuing through product qualification and screening.
QML devices offer ease of procurement by eliminating the need to create detailed specifications and offer benefits of improved quality and cost savings through standardization.
RELIABILITY
Honeywell understands the stringent reliability requirements that space and defense systems require and has extensive experience in reliability testing on programs of this nature. This experience is derived from comprehensive testing of VLSI processes. Reliability attributes of the RICMOSTM process were characterized by testing specially designed irradiated and non-irradiated test structures from which specific failure mechanisms were evaluated. These specific mechanisms included, but were not limited to, hot carriers, electromigration and time dependent dielectric breakdown. This data was then used to make changes to the design models and process to ensure more reliable products. In addition, the reliability of the RICMOSTM process and product in a military environment was monitored by testing irradiated and non-irradiated circuits in accelerated dynamic life test conditions. Packages are qualified for product use after undergoing Groups B & D testing as outlined in MIL-STD-883, TM 5005, Class S. The product is qualified by following a screening and testing flow to meet the customer's requirements. Quality conformance testing is performed as an option on all production lots to ensure the ongoing reliability of the product. 9
SCREENING LEVELS
Honeywell offers several levels of device screening to meet your system needs. "Engineering Devices" are available with limited performance and screening for breadboarding and/or evaluation testing. Hi-Rel Level B and S devices undergo additional screening per the requirements of MILSTD-883. As a QML supplier, Honeywell also offers QML Class Q and V devices per MIL-PRF-38535 and are available per the applicable Standard Military Drawing (SMD).
HC6856
PACKAGING
The 32K x 8 SRAM is offered in a custom 36-lead flat pack (FP), 28-Lead FP, or standard 28-lead DIP. Each package is constructed of multilayer ceramic (Al2O3) and features internal power and ground planes. The 36-lead FP also features a non-conductive ceramic tie bar on the lead frame. The purpose of the tie bar is to allow electrical testing of the device, while preserving the lead integrity during shipping and handling, up to the point of lead forming and insertion. Ceramic chip capacitors can be mounted to the package by the user to maximize supply noise decoupling and increase board packing density. These capacitors attach directly to the internal package power and ground planes. This design minimizes resistance and inductance of the bond wire and package, both of which are critical in a transient radiation environment. All NC (no connect) pins must be connected to either VDD, VSS or an active driver to prevent charge build up in the radiation environment.
28-LEAD DIP & FP PINOUT
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
36-LEAD FLAT PACK PINOUT
VSS VDD A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 NC VDD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VSS VDD NWE CE A13 A8 A9 A11 NOE A10 NCS DQ7 DQ6 DQ5 DQ4 DQ3 VDD VSS
Top View
VDD NWE A13 A8 A9 A11 NOE A10 NCS DQ7 DQ6 DQ5 DQ4 DQ3
Top View
36-LEAD FLAT PACK (22017194-001)
E
1
Top Side
b (width)
D G
e (pitch)
H
L
L
Ceramic Body
J A
Optional Standoff
Kovar Lid [3]
NonConductive Tie-Bar
0.004 N M
I
C
X VDD VSS
Optional Capacitors
VDD
VSS
S A b C D E e F G H I J L
All dimensions are in inches [1]
0.095 0.010 0.008 0.002 0.005 to 0.0075 0.650 0.010 0.630 0.007 0.025 0.002 [2] 0.425 0.005 [2] 0.525 0.005 0.135 0.005 0.030 0.005 0.080 typ. 0.285 0.015 M N O P R S T U V W X Y 0.008 0.003 0.050 0.010 0.090 ref 0.015 ref 0.075 ref 0.113 0.010 0.050 ref 0.030 ref 0.080 ref 0.005 ref 0.450 ref 0.400 ref
F
Y
1
1
O V
W P R T U
[1] Parts delivered with leads unformed [2] At tie bar [3] Lid tied to VSS
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HC6856
28-LEAD FLAT PACK (22017362-001)
E 1 b
(width) Optional capacitors in cutout VDD VSS VDD
All dimensions in inches 1
A b C D e E E2 E3 F G L Q S U V W X Y Z 0.135 0.015 0.015 0.002 0.004 to 0.009 0.720 0.008 0.050 0.005 [1] 0.530 0.008 0.420 0.008 0.055 ref 0.650 0.005 [2] 0.050 0.005 0.295 min [3] 0.026 to 0.045 0.035 0.010 0.065 ref 0.300 ref 0.050 ref 0.030 ref 0.100 ref 0.080 ref
TOP VIEW
e
(pitch)
BOTTOM VIEW
S Z X W Y V U
F
L
Q
G
A
Kovar Lid [4]
Cutout Area
Ceramic Body
C
Lead Alloy 42
D
E2
E3
[1] [2] [3] [4]
BSC - Basic lead spacing between centers Where lead is brazed to package Parts delivered with leads unformed Lid connected to VSS
28-LEAD DIP (22017502-001)
For 28-Lead DIP description, see MIL-STD-1835, Type CDIP2-T28, Config. C, Dimensions D-10
DYNAMIC BURN-IN DIAGRAM
STATIC BURN-IN DIAGRAM
VSS
F16 F7 F6 F5 F4 F3 F2 F8 F13 F14 F1 F1 F1
R R R R R R R R R R R R R
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
VSS VDD A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQO DQ1 DQ2 VDD VSS
VSS VDD NWE* CE* A13* A8 A9 A11 NOE A10 NCS DQ7 DQ6 DQ5 DQ4 DQ3 VDD VSS
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
VDD
R R R R R R R R R R R R R R
VDD VSS
R R R R R R R R R R R R R
F0 F17 F15 F12 F11 F10 F17 F9 F17 F1 F1 F1 F1 F1
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
VSS VDD A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQO DQ1 DQ2 VDD VSS
VSS VDD NWE* CE* A13* A8 A9 A11 NOE A10 NCS DQ7 DQ6 DQ5 DQ4 DQ3 VDD VSS
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
R R R R R R R R R R R R R R
VSS VDD = 6.5V, R 10 K, VIH = VDD, VIL = VSS Ambient Temperature 125 C, F0 100 KHz Sq Wave Frequency of F1 = F0/2, F2 = F0/4, F3 = F0/8, etc.
32K x 8 SRAM
VSS VDD = 5.5V, R 10 K Ambient Temperature 125 C
NOTE -- *Denotes package pinout option dependent (28-Lead DIP/FP diagrams not shown but have similar connections)
11
32K x 8 SRAM
HC6856
ORDERING INFORMATION (1) H C 6856/1
PART NUMBER Pinout options (2) PROCESS C=CMOS SOURCE H=HONEYWELL
X
Q
SCREEN LEVEL (1) V=QML Class V Q=QML Class Q S=Level S B=Level B E=Engr Device (4)
H
Z
C
40
SOFT ERROR RATE Z=<1x10-10 upsets/bit-day A=<1x10-9 upsets/bit-day (3) C=<1x10-7 upsets/bit-day - =No SER Guaranteed
SPEED (5) 60 ns 40 ns 35 ns
PACKAGE DESIGNATION W=36-Lead FP X=36-Lead FP, with standoff Y=36-Lead FP, with standoff & caps N=28-Lead FP R=28-Lead DIP - = Bare Die (No Package)
TOTAL DOSE HARDNESS R=1x105rad(SiO2) F=3x105 rad(SiO2) H=1x106 rad(SiO2) N=No Level Guaranteed
INPUT BUFFER TYPE C=CMOS Level T=TTL Level
(1) Orders may be faxed to 612-954-2051. Please contact our Customer Logistics Department at 612-954-2888 for further information. (2) Pinout options: 36-Lead FP 28-Lead FP & DIP pin 32 pin 33 pin 34 HC6856/1 A13 CE NWE JEDEC Pinout HC6856/2 CE NWE A13 N/A (3) SER <1E-10 u/b-d from -55 to 80C. (4) Engineering Device description: Parameters are tested from -55 to 125C, 24 hr burn-in, no radiation guaranteed. (5) Only specified for Engineering Devices. Number defines worst case maximum Write Cycle time in nano-seconds (ns). Contact Factory with other needs.
To learn more about Honeywell Solid State Electronics Center, visit our web site at http://www.ssec.honeywell.com
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
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Price & Availability of HC6856NQRAC35

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